Note that there is a phenomenon called CdV/dt-induced turn-on that is known to cause cross-conduction, especially in low-voltage VRM-type applications — despite sufficient dead time apparently being present. For example, in a synchronous Buck, if the top N-channel FET turns ON very suddenly, it will produce a high dV/dt on the Drain of the bottom FET. That can cause enough current to flow through the Drain-to-Gate capacitance (Cgd) of the bottom FET, which can produce a noticeable voltage bump on its Gate, perhaps enough to cause it to turn ON momentarily (but may be only a partial turn-on). This will therefore produce an unexpected FET overlap, one apparent perhaps only through an inexplicably low-efficiency reading at light loads.
To avoid this scenario, we may need to do one or more of the following:
- Slow down the top FET
- Have good PCB layout (in the case of controllers driving external FETs) to ensure that the Gate drive of the lower is held firmly down.
- Design the Gate driver of the lower FET to be “stiff”
- Choose a bottom FET with slightly higher Gate threshold, if possible.
- Choose a bottom FET that has a low Cgd.
- Choose a bottom FET with a very small internal series Gate resistance.
- Choose a bottom FET with high Gate-to-Source capacitance (Cgs).
- Perhaps even try to position the decoupling capacitor positioned on the input rail slightly far away from the FETs (even a few millimeters of trace inductance can help) so that despite slight overlap, at least the cross-conduction current flowing during the (voltage) overlap time gets limited by the intervening PCB trace inductances.